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Altera_Forum
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9 years ago

Unreliable D-FLOP

I've created a basic D-FLOP with a MAX3000 device. The FF clock input is driven by a debounced switch and the CPLD has an external reset chip and the FF reset input is mapped to the GCLR pin. When I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

FvM,

I tacked a larger capacitor across the .1 and tried again. This time it worked perfectly. I'm puzzled because I've used this circuit successfully in the past, but my scope isn't capable of capturing the transients you talked about so I wouldn't have seen them. Thank you sir!