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Altera_Forum
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9 years ago

Unreliable D-FLOP

I've created a basic D-FLOP with a MAX3000 device. The FF clock input is driven by a debounced switch and the CPLD has an external reset chip and the FF reset input is mapped to the GCLR pin. When I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It's a poor debounce circuit. RC time constant of 1 ms does not surely filter all bounce pulses. Bigger problem is that the capacitor is discharged without current limiting resistor, causes contact arcing and oscillations with possibly multiple edges in the 10 to 100 MHz range which can well trigger the FF twice.