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FST's avatar
FST
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5 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi

We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface..

On our board we use the Jam STAPL Byte-Code Player Version 2.2 software to program the Serial Configuration Device via JTAG.

The programming is working, but propably during the time of access to the Serial Configuration Device via the Serial Flash Loader (SFL) some IOs of the FPGA do not have anymore this Weak Pull-ups as we expect.

(E.g. when I start programming the output (Pin B4) gets first input with weak Pull-up for a while and then just input or input with Weak Pull-down before it gets again ouput at the end.)

Is there any explanation of this behavior?

Best Regards

Fredi

P.S.

As I remember, we had similar effects in a old project, but only when we generated the .jbc file with Quartus newer then 13.1. Maybe that helps to find the problem.

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    • FST's avatar
      FST
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi YuanLi

      In our design the unused IOs are already set as input tri-stated with weak pull-up. And actually the Pin B4 is used as an output.

      What about the IOs after the SFL from the generated .jbc file is loaded via JTAG and active? Can we also define them in this state of the programming?

      As I wrote during programming of the Config. Flash via JTAG-SFL(Serial Flash Loader)-ASMI(Actice Serial Memory Interface), this output has not anymore a weak pull-up.

      Best Regards

      Fredi

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi FST,


    Yes all pin are pulled to HIGH Z during configuration mode. When the device is booted successfully, unused pin will remain the same as what is set in Quartus. Meanwhile, used pin will go back to the state which is set in the design.


    Regards,

    Bruce


    • FST's avatar
      FST
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi Bruce

      What you describe is correct. But I was talking about the pin state during programming of the Configuration Memory via JTAG-SFL-ASMI.

      It seems that when the SFL is active, some IOs are not anymore with weak pull-ups.

      Or do you say, that we can define the IOs of this SFL bridge, which gets loaded first, somehow in Quartus. How do we have to do it?

      Best Regards

      Fredi

      P.S. sorry for my poor english