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FST's avatar
FST
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4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi FST,


Yes all pin are pulled to HIGH Z during configuration mode. When the device is booted successfully, unused pin will remain the same as what is set in Quartus. Meanwhile, used pin will go back to the state which is set in the design.


Regards,

Bruce


FST's avatar
FST
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4 years ago

Hi Bruce

What you describe is correct. But I was talking about the pin state during programming of the Configuration Memory via JTAG-SFL-ASMI.

It seems that when the SFL is active, some IOs are not anymore with weak pull-ups.

Or do you say, that we can define the IOs of this SFL bridge, which gets loaded first, somehow in Quartus. How do we have to do it?

Best Regards

Fredi

P.S. sorry for my poor english