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FST
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4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
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FST
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4 years ago

Hi YuanLi

In our design the unused IOs are already set as input tri-stated with weak pull-up. And actually the Pin B4 is used as an output.

What about the IOs after the SFL from the generated .jbc file is loaded via JTAG and active? Can we also define them in this state of the programming?

As I wrote during programming of the Config. Flash via JTAG-SFL(Serial Flash Loader)-ASMI(Actice Serial Memory Interface), this output has not anymore a weak pull-up.

Best Regards

Fredi