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FST's avatar
FST
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4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Fendi,


Sorry for being late, i was in discussion with internal team about this. From the timing diagram, it seems like the pin is pulled down during image file (JBC File) programming.


Also, you mentioned that the JBC file generated after v13.0, all pin are pulled-up during programming, but now, when generated with v19.1, all pin are pulled-down during programming?


Regards

Bruce


FST's avatar
FST
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4 years ago

Hi Bruce

I do not know whether all Pins are low during programming of the Configuration Flash via JTAG and SFL Bridge. At least Pin R7 is it. Why? And can we change that?

We have not tried this project with Quartus v13.1 yet. That was some years ago where we had similar issues. But maybe it was something else. I will ask your designer to try with Quartus v13.1.

Is from your side something different between v13.1 and v19.0 according automatic added SFL Bridge?

Regards

Fredi