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FST
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4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
FST's avatar
FST
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4 years ago

Hi Bruce

In my picture above we can see that the chipselect of the configuration memory ('CSO' Pin D2) is toggling during the time when the FPGA Pin R7 is low.

As the programming basically is working, I assume we see the access to the configuration memory via JTAG and this Enhanced Serial Flash Loader (SFL) during this time.

But somehow the Pin R7 is not pulled high during this time.

Best Regrads

Fredi