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Altera_Forum's avatar
Altera_Forum
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14 years ago

Unable to establish link between PCS and PHY in SGMII mode

Hi,

I was trying to use System Console for setting up Triple Speed Ethernet design in SGMII mode. I was able to successfully configure the MAC and PHY registers. After this i configured the PCS registers ( scratch, if_mode, control) . When i try to read status and partner_ability registers, i am unable to get a favorable result.

In status Register the 3rd bit link_status is zero, when i read it. As per user guide this means link synchronization is lost.

Similarly 16th bit of partner_ability Register copper_link_status is also zero. As per user guide this means copper interface link is down.

I was able to verify the PHY link is up with the following characteristics by reading PHY Specific Status Register.

PHY Link Up.

PHY Speed and Duplex Resolved.

PHY operating in Full Duplex mode.

PHY operating Speed 1000Mbps

Any idea why PCS is failing. Any pointers in this direction will be really helpful

Thanks in advance

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    I have one more doubt.

    How can i verify the MAC registers that i have set does not create any issues.

    Here are the registers that i set and read out onto the console.

    TSE MAC Rev = 0x00000a01

    TSE MAC read Scratch = 0xaaaaaaaa

    Command Config = 0x0100001b

    MAC Address 0 = 0x22334450

    MAC Address 1 = 0x0000ee11

    Frame Length = 0x000005dc

    Pause Quanta = 0x0000ffff

    RX Section Empty = 0x00000000

    RX Section Full = 0x00000000

    TX Section Empty = 0x00000000

    TX Section Full = 0x00000000

    RX Almost Empty = 0x00000008

    RX Almost Full = 0x0000000e

    TX Almost Empty = 0x00000008

    TX Almost Full = 0x00000003

    MDIO Address 0 = 0x00000000

    MDIO Address 1 = 0x00000000

    Regiter Status = 0x00000000

    TX IPG Length = 0x0000000c

    TX Command Status = 0x00000000

    RX Command Status = 0x00000000

    Thanks in advance
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    Can anyone tell me why this issue may be happening when configuring the PCS registers.

    Thanks in advance
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I find the signals led_link and led_col to be always high in Signal Tap. I am using a Terasic DE4 board.

    For the reference ethernet design using Nios, when i connect the ethernet cable i find the LEDs corresponding to Rx and Tx to be blinking all the time. But for the design i am doing with System console the Rx LED blinks for some time, while the Tx never blinks.

    My PHY configuration seems to be working fine, but in PCS a successful link synchronization does not appear to be happening. Any idea why this could be happening?.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Did you make any progress with this? I'm also trying to get the tse at the DE4 to work. I can see the rx-led blinking when I send a UDP packet from my host pc to the FPGA, but there are no data at all dropping out of the FIFOs.

    With the NIOS-TSE it works. Now I configured my TSE exactly in the same way as in the nios, I dumped the whole configuration memory from the NIOS-TSE and configured my stand-alone TSE with this data. I also wrote the config register (byte offset 0x008) not until the end as it is mentioned in the TSE user guide. I still can't get data out of the TSE.

    Any ideas?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I finally made it: In my first attemp i read out the ethernet configuration memory from the working nios project, but configuring the TSE with this data was also not working.

    Now, I dumped exactly what data are written to what addresses at the tse configuration interface. Than I did exactly the same in my tse-only project, and now its working.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you very much. This information has been very helpful in helping me to resolve my issue.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Kairue

    I'm having the same problem as you had. I can't get a working connection between the MAC and the PHY. A link synchronization cannot be established. Can you provide me with the registers you finally had to set in order to get it working? I would really appreciate your help!

    Thanks

    Marcel
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I think this will work for the DE4 only, maybe also for other TSE cores with SGMII interface, PCS, embedded PMA and external FIFOS.

    I basicly dumped the register addresses and data that are written from the DE4-Ethernet Demo with the Nios to two ROMS. Now I run through those memorys from address 0x0 to 0x7E at my own setup sequence, reading addresses and data step by step and give them to the configuration interface at the TSE core. Here are the dumped memory contents. I know that some commands seem to be redundant, but at least its working.

    Regards,

    Kai

    Addresses 

    
      :   00000010;
    021  :   00000094;
    022  :   00000002;
    023  :   00000005;
    024  :   0000000B;
    025  :   0000000C;
    026  :   0000000D;
    027  :   0000000E;
    028  :   00000009;
    029  :   0000000A;
    02A  :   00000007;
    02B  :   00000008;
    02C  :   0000003A;
    02D  :   0000003B;
    02E  :   00000002;
    02F  :   00000003;
    030  :   00000004;
    031  :   00000010;
    032  :   000000A0;
    033  :   00000010;
      :   000000A9;
      :   00000010;
      :   000000A4;
      :   00000010;
      :   000000A4;
      :   00000010;
      :   000000A0;
      :   00000010;
    064  :   00000094;
      :   00000010;
    068  :   000000A0;
    069  :   00000002;
    06A  :   00000005;
    06B  :   0000000B;
    06C  :   0000000C;
    06D  :   0000000D;
    06E  :   0000000E;
    06F  :   00000009;
    070  :   0000000A;
    071  :   00000007;
    072  :   00000008;
    073  :   0000003A;
    074  :   0000003B;
    075  :   00000002;
    076  :   00000003;
    077  :   00000004;
      :   00000000;
    Data 

    
    000  :   00000000;
    001  :   00000001;
    002  :   00000002;
    003  :   00000003;
    004  :   00000004;
    005  :   00000005;
    006  :   00000006;
    007  :   00000007;
    008  :   00000008;
    009  :   00000009;
    00A  :   0000000A;
    00B  :   0000000B;
    00C  :   0000000C;
    00D  :   0000000D;
    00E  :   0000000E;
    00F  :   0000000F;
    010  :   00000010;
    011  :   00000011;
    012  :   00000012;
    013  :   00000013;
    014  :   00000014;
    015  :   00000015;
    016  :   00000016;
    017  :   00000017;
    018  :   00000018;
    019  :   00000019;
    01A  :   0000001A;
    01B  :   0000001B;
    01C  :   0000001C;
    01D  :   0000001D;
    01E  :   0000001E;
    01F  :   0000001F;
    020  :   00000001;
    021  :   00000003;
    022  :   00002003;
    023  :   000005EE;
      :   00000008;
    027  :   00000003;
    028  :   000007F0;
    029  :   00000000;
    02A  :   000007F0;
    02B  :   00000000;
    02C  :   00040000;
    02D  :   02000000;
    02E  :   04000003;
    02F  :   FFED0702;
    030  :   000015ED;
    031  :   00000000;
    032  :   00001140;
    033  :   00000000;
      :   00000F00;
      :   00000000;
      :   000001E1;
      :   00000000;
      :   000001E1;
      :   00000000;
    041  :   00001140;
    042  :   00001340;
    043  :   00000000;
    044  :   00000001;
    045  :   00000002;
    046  :   00000003;
    047  :   00000004;
    048  :   00000005;
    049  :   00000006;
    04A  :   00000007;
    04B  :   00000008;
    04C  :   00000009;
    04D  :   0000000A;
    04E  :   0000000B;
    04F  :   0000000C;
    050  :   0000000D;
    051  :   0000000E;
    052  :   0000000F;
    053  :   00000010;
    054  :   00000011;
    055  :   00000012;
    056  :   00000013;
    057  :   00000014;
    058  :   00000015;
    059  :   00000016;
    05A  :   00000017;
    05B  :   00000018;
    05C  :   00000019;
    05D  :   0000001A;
    05E  :   0000001B;
    05F  :   0000001C;
    060  :   0000001D;
    061  :   0000001E;
    062  :   0000001F;
    063  :   00000001;
    064  :   00000003;
    065  :   00000000;
    066  :   00000001;
    067  :   00000000;
    068  :   00001140;
    069  :   00002003;
    06A  :   000005EE;
      :   00000008;
    06E  :   00000003;
    06F  :   000007F0;
    070  :   00000000;
    071  :   000007F0;
    072  :   00000000;
    073  :   00040000;
    074  :   02000000;
    075  :   04000033;
    076  :   FFED0702;
    077  :   000015ED;
      :   00000000;
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    thank you very much for your quick reply. Finally it seems I got it working altough I had another issue. In my original design I didn't add an altgx_reconfig block because I thought I don't need to. This obviously was big mistake. In the example design they implemented this IP and so did I .... after 2 days of trying! Now I can send a package and capture it with wireshark. However, I still don't have a clue what this block actually does. But hopefully google will help me ....

    cheers

    Marcel