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Altera_Forum
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15 years ago

Unable to establish link between PCS and PHY in SGMII mode

Hi, I was trying to use System Console for setting up Triple Speed Ethernet design in SGMII mode. I was able to successfully configure the MAC and PHY registers. After this i configured the PCS...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Did you make any progress with this? I'm also trying to get the tse at the DE4 to work. I can see the rx-led blinking when I send a UDP packet from my host pc to the FPGA, but there are no data at all dropping out of the FIFOs.

With the NIOS-TSE it works. Now I configured my TSE exactly in the same way as in the nios, I dumped the whole configuration memory from the NIOS-TSE and configured my stand-alone TSE with this data. I also wrote the config register (byte offset 0x008) not until the end as it is mentioned in the TSE user guide. I still can't get data out of the TSE.

Any ideas?