Unable to drive multiple PLL's with the same clock on Cyclone II FPGA

Hi

I'm having problems using a single input clock for multiple PLL's on a Cyclone II FPGA. This is to work around the fact that I can't get the desired output clock frequencies for my design by using a single PLL. My design synthesises alright but when it comes to the fitter, it generates an error telling me that I can't drive multiple PLL's with the same clock.

I have tried using separate clock buffers, using the Altera 'clkctrl' megafunction. Alhough this gets rid of the old error, it gives a new one saying that the PLL clock inputs cannot be fed by global clocks. I have even tried making a simple buffer of my own and then making multiple instances of it. I still get an error saying that the clock input of the PLL's must be fed by a non-inverted clock pin (I think).

My design doesn't use any cascaded PLL's and I know it should be possible to do this as PLL's are supposed to be independent of each other.

Any help will be appreciated.