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Altera_Forum
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16 years ago

Unable to drive multiple PLL's with the same clock on Cyclone II FPGA

Hi I'm having problems using a single input clock for multiple PLL's on a Cyclone II FPGA. This is to work around the fact that I can't get the desired output clock frequencies for my design by...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks!! This has fixed the issue although I had to add some extra ports to my design to accomodate each clock. Will be using a Cyclone II for development and a Cyclone III for the final design; shouldn't need these extra ports then.