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Altera_Forum
Honored Contributor
Honored ContributorUnable to drive multiple PLL's with the same clock on Cyclone II FPGA
Hi I'm having problems using a single input clock for multiple PLL's on a Cyclone II FPGA. This is to work around the fact that I can't get the desired output clock frequencies for my design by...
Altera_ForumHonored Contributor
Honored ContributorIn a short, each PLL requires individual dedicated clock inputs with Cyclone II. No workaround.
