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Honored Contributor
Honored ContributorUnable to drive multiple PLL's with the same clock on Cyclone II FPGA
Hi I'm having problems using a single input clock for multiple PLL's on a Cyclone II FPGA. This is to work around the fact that I can't get the desired output clock frequencies for my design by...
Altera_ForumHonored Contributor
Honored ContributorYou need to look at the cyclone II user's guide:
Specifically look at table 7-3 on page 7-6 in the following document: http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf You see which clock input pins have access to which PLLs in the device. Jake
