Occasional Contributor
Regular ContributorHi,
Do you know I could replicate the issue using the GHRD? Or if you could, maybe change the settings exactly the same but using the GHRD project, and see if the error pops up. You may want to also check the connection in the Platform Designer as well between the GHRD and yours.
Occasional ContributorHi,
except for the fact that our design uses a different circuit the GHRD seams to share the same settings. Strangely enough I can't replicate these errors using the GHRD, aldough I need to admit that I only copied the sdmmc constraints so far. I copied the offending constrains using a text editor, so they should match. Having only the sdmmc constraints enabled in the actual design doesn't result in a successful build dough so it shouldn't matter that I only transferred those to the GHRD yet.
My IP settings and conduits in platform designer are exactly identical to the ones in the GHRD except for the following things:
* My HPS settings do not include 7 GPIO pins (instead we use 0)
* My HPS settings do not export USB to the board
* We don't use the Avalon Memory mapped pipeline. Instead we use a custom AXI lite slave.
Except for the fact that my top module is written in VHDL instead of Verilog they really look quite similar. All connections from the HPS to outside are all plain wire assignments.
Is there any obvious documentation I missed? I studied the GHRD quite extensive by now and am really confused why it works in there but not in my design. Shall I post parts of my design? What would be the relevant parts beside the qsys, qsf and sdc files and the top module?
Thanks for your patience!
Regular ContributorHi,
Can you share both the design here that you compiled, the working one and the not working one?
Preferably if you can archived the project and upload both here, I want to check it from my side and replicate it.
Occasional ContributorHi,
We already found a work around for this issue. As it turned out it had something to do with the automatic timing estimations. Disabling the automatic generation and using a manually crafted file solved it.
New ContributorHello,
This thread is a bit old, but I've run into the same issue and hope I can get some clarification on the solution.
How is the automatic generation disabled? Also, are there any specifics about the manually crafted timing and what this means? Are these SDC constraints?
Hope someone can help.
Ian
