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Altera_Forum's avatar
Altera_Forum
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13 years ago

Unable to assign PLL*out as LVDS IO standard in Cyclone III

Hello All,

I am unable to assign PLL*out pin to LVDS IO standard in Cyclone 3 device.

I have already designed the board with this pinning.

The board has Cyclone 3 device and is interfaced to TRXAESMM transceiver for high speed link.

Device: EP3C120F484C8

Pins:

E5 (PLL3_CLKOUTp) -> connected to RX+ (of TRXAESMM spf module)

E6 (PLL3_CLKOUTn) -> connected to RX- (of TRXAESMM spf module)

Error Message:

Editing location assignment is not successfull. Incompatible IO standard

or

Pin_E5 cannot be assigned to LVDS IO standards

Pin_E6 cannot be assigned to LVDS IO standards

Please guide me. I am in trouble if i dont get this solved as my boards are already on there way.

note that i have successfully done the same kind of assignment in stratixii device. it works just fine.

Best Regards,

VVP

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Most likely reason: wrong bank voltage. B8 voltage of 2.5V is required.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks for the response.

    B8 is at 2.5V.

    Only E5 should be LVDS.

    Please let me know your suggestion.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello,

    I see that this problem is seen with PLL*_out pins.

    However , i have already checked with stratix II device and PLL out pin assigned as LVDS works just fine.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Please let me know whats wrong with my assignment and how i can get rid of this problem.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hello Friends,

    Please let me know if u need any info from my side.

    The board is designed with this pinnig already.

    Is there any alternative that i can adopt to to make this work.

    BEST REGARDS,

    vvp
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I was able to check the issue in Quartus today. The problem is that the PLLOUT pins are top/bottom pins that don't support true LVDS output standard, only LVDS_E_3R using external resistors.

    The problem reveals immediately if you assign the pins in the Pin Planner tool that shows the available I/O standards for each pin.

    Frank