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Altera_Forum
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13 years ago

Unable to assign PLL*out as LVDS IO standard in Cyclone III

Hello All, I am unable to assign PLL*out pin to LVDS IO standard in Cyclone 3 device. I have already designed the board with this pinning. The board has Cyclone 3 device and is interfaced...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I was able to check the issue in Quartus today. The problem is that the PLLOUT pins are top/bottom pins that don't support true LVDS output standard, only LVDS_E_3R using external resistors.

The problem reveals immediately if you assign the pins in the Pin Planner tool that shows the available I/O standards for each pin.

Frank