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Altera_Forum's avatar
Altera_Forum
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10 years ago

Unable to Address Full Memory Range in Mixed Width Dual Port RAM Module

I used MegaWizard to create a mixed width dual port RAM module with the following configuration:

Port A: 8x256

Port B: 32x64

Single Clock

When I simulate the module in ModelSim, everything looks great, but when I program my FPGA, I can only access up to address 0x7F on Port A. Addresses at 0x80 and above that seem to wrap around to address range starting from 0x20. I've checked the fitter report, and it shows that the RAM was implemented as defined (Implementation Bits = 2048). I'm wondering if I'm missing something obvious.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Found out what the issue was; clock domain synchronization 101. The signals from the microcontroller at RAM port A were not synchronized to local FPGA clock. Added synchronizers are everything works now. Signal Tap is awesome, by the way.