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Honored Contributor
Honored ContributorUnable to Address Full Memory Range in Mixed Width Dual Port RAM Module
I used MegaWizard to create a mixed width dual port RAM module with the following configuration: Port A: 8x256 Port B: 32x64 Single Clock When I simulate the module in ModelSim, everythi...
Altera_ForumHonored Contributor
Honored ContributorFound out what the issue was; clock domain synchronization 101. The signals from the microcontroller at RAM port A were not synchronized to local FPGA clock. Added synchronizers are everything works now. Signal Tap is awesome, by the way.
