uart communications

Hey all, I finally solved my problem today. Using a multimeter, oscillascope, 2 different serial cables and a soldering iron.

module test(input  CLOCK_50,
	output  LEDR,
	output UART_TXD,
	input  UART_RXD,
	input  SW
	);
	
	wire serial_clk;
	new_clock pll(.inclk0(CLOCK_50), .c0(serial_clock));
	
	reg  waiter = 12'b0000000000000; //counter to reduce clock rate
	//reg  waiter = 13'b0000000000000; //counter to reduce clock rate
	reg  state = 4'b0000; //current state. 0 = start bit, 1-8 = data bits, 9 = stop bit, other = ended
	reg data = 1'b1; //start high = idle state
	reg clk_new = 0; //changes the state of an led every time a bit is sent
	
	reg  origData = 48'h00_4F_4C_4C_45_48; //HELLO in ascii, little endian
	reg  currData;
	reg started = 0;
	assign LEDR = data; //led outputs current data bit
	assign LEDR = SW; //led outputs status of a switch
	assign LEDR = clk_new; //led shows when new bit is sent
	assign UART_TXD = data; //assert the transmit wire to the data bit
	
	always @(posedge serial_clock) //every clock tick
	begin
		//if (waiter == 27'b111111111111111111111111111) //1/2 times a second
		if (waiter == 12'b1100_0011_0100) //9600 times a second (aprox)
		begin
			waiter <= 12'b000000000000; //reset counter
			if (started == 0) //have we not started yet?
			begin
				if (SW) //start if switch 0 is high
				begin
					started <= 1;
					currData <= origData; //set the current data register to be the original data register
				end
			end
			else //we have started
			begin
				clk_new <= !clk_new; //change clock led
				if (currData == 48'd0 && state == 4'h0) //end of transmit
				begin
					data <= 1'b1; //idle bit
					if (!SW) //if switch 0 is low, then reset to not started
					begin
						started <= 1'b0;
					end
				end
				else
				begin				
					if (state == 4'h0) //start bit
					begin
						data <= 1'b0;			
					end
					else if(state == 4'h9) //stop bit
					begin
						data <= 1'b1;
					end
					else if(state < 4'h9) //data bits
					begin
						data <= currData; //get first bit
						currData <= currData >> 1; //right shift, so as first bit is the next bit to send
					end
						
					if (state == 4'h9) //update state
					begin
						state <= 4'h0;
					end
					else
					begin
						state <= state + 1'b1;
					end
				end //end data left to transmit
			end //end started == 1
		end //end if (waiter == ...)
		else
		begin
			waiter <= waiter + 1'b1;  //inc waiter
		end
	end //end always @...
	
endmodule

I come across a coding in verilog for the UART....

I don't exactly understand the question. TxD_busy is nothing to connect at the external UART interface. It's an internal signal to inform the data source when the UART is ready to accept the next character.

ok then how bout the inputs....must i connect normal switch as inputs from the altera de-2 board