Two clock domains in the same procces

The module clock is CLK = 120 Mhz.

The milliseconds counter clock is MS_CLK = 100 Mhz.

I count milliseconds

constant TICKS_FOR_1MS : std_logic_vector(31 downto 0) := X"000186A0"; --100 Mhz
process (MS_CLK)
begin

    if (rising_edge(MS_CLK)) then
        
         if (count_reset= '1') then
             ticks_counter <= (others => '0');
             ms_counter <= (others => '0');
         else
            ticks_counter <= ticks_counter + '1';
            if (ticks_counter = TICKS_FOR_1MS) then
                  ticks_counter <= (others => '0');
                  ms_counter <= ms_counter + '1';
            end if;
        end if;

    end if;   
end process;

The problem is - the signal count_reset is changed in another process that clocked with CLK. How to synchronize those signals?