New ContributorTSE Timing constraints
I have a couple questions regarding the timing constraints of the Triple Speed Ethernet IP Core.
Background:
Quartus II 11.1
20 mhz clk input pin sources to PLL
PLL1 sources: 125 mhz clk 90 deg phase shifted (rgmii_tx_clk) - RGMII clk to the phy , phase shifted
sources: 125 mhz clk 0 deg phase shifted (tx_data_clk) - clk for RGMII TX data registers
sources: 100 mhz clk 0 deg phase shifted (clk) - clk for FIFO (AST) and clk for core config
Clks were chosen based on reocmmendations for 32 mb fifo variant and 1gb
I am using 1gb Small MAC variant of the IP core.
Since im using PLL to source the clks, the SDC files generated by the core were giving me trouble since those files expect clks to be at the top level not from pll .
For the small MAC variant, these constraints simply constrain the declared clocks and set asynchronous groups between each. Is this correct?
I added all my constraints to the top level and added RGMII constraints according to AN477
and added asynchronous clock groups separating rgmii_tx clk + tx_data clk from clk.
Is it safe to assume that rgmii_tx_clk and tx_data_clk are asynchronous from clk?
Timing report shows violations due to the 100 mhz to 125 mhz relationship. I assume there are internal CDCs to handle the variance between core clk and rgmii clks. Would setting asynchronous clock groups / or false paths between the different domains affect these synchronizers?
Thanks
