Forum Discussion
jayrflare
New Contributor
New ContributorTSE Timing constraints
I have a couple questions regarding the timing constraints of the Triple Speed Ethernet IP Core.
Background:
Quartus II 11.1
20 mhz clk input pin sources to PLL
PLL1 sources: 125 mhz clk 90 ...
IntelSupport
Contributor
ContributorHi Justin,
Just to confirm Firstly, Is the CDC occur within TSE IP?
Also. can you migrate to latest version if possible? 11.1 is quite old and might be hard to support.
jayrflareNew Contributor
New ContributorHi, that is the question i have here. My assumption is that streaming clocks and core clock are asynchronous to the RGMII Tx clocks WITHIN the TSE IP. I do cannot confirm since I cannot see logic within the IP.
I cannot migrate to newer version due to current licensing (safety package). Regardless, i believe the implementation of the CDC will be the same throughout all versions of TSE IP.
