TSE Timing constraints

Hi,

Thank you for the response.

So within the Intel TSE IP, tx_data_clock, and rgmii_tx clks ARE asynchronous from clk. So my assumption is correct that it is okay to use clock groups to separate them.

Are there any other timing constraints that the Intel TSE needs aside from setting clock groups, and constraining each clk on the top level?

How would i handle these constraints according to the article when i dont know what registers are being used for clock crossing within the intel TSE IP?

I am unsure what i would put as data_a and data_b

So for my example, what registers would need to have a net delay and max skew constraint when considering the tx_data_clock to clk relationship where:

Tx_data_clock is 125 mhz nonshifted clock sourcing the RGMII TX data registers

Clk is 100 mhz clk sourcing TSE control and Avalon ST fifo registers

Thanks