Forum Discussion
jayrflare
New Contributor
New ContributorTSE Timing constraints
I have a couple questions regarding the timing constraints of the Triple Speed Ethernet IP Core.
Background:
Quartus II 11.1
20 mhz clk input pin sources to PLL
PLL1 sources: 125 mhz clk 90 ...
IntelSupport
Contributor
ContributorHi jayrflare,
rgmii_tx_clk and tx_data_clk are asynchronous from clk?
- In this scenario, where the clocks are derived from the same source, static timing analysis is possible and safe to assume it is asynchronous. You may see below KDB on CDC constrain.
https://www.intel.com/content/www/us/en/support/programmable/articles/000080400.html
