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Altera_Forum's avatar
Altera_Forum
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15 years ago

trying to constrain external clock driver (TQ), searching help

Hello,

as the title already reveals, I am trying to constrain my external hardware in the TimeQuest. After my "sysclk_out" in in my design there is a clock driver on my board, that I would like to constrain.

It is a CDCVF2505PW, the datasheet can be found at the ti website: http://focus.ti.com/lit/ds/symlink/cdcvf2505.pdf

I have added a sketch of the system to this thread that shows the path I want to constrain. Unfortunately, I did not know how to calculate or read Tsu/Th from the datasheet.

Can someone with some experience explain or give me the solution to constrain this path, please.

Thanks, Peter.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I don't think there is a Tsu/Th to a clock divider. Tsu/Th are concepts of data related to a clock, where this is "just a clock". In general you don't constrain this.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The CDCVF2505PW is a PLL-based clock driver, as such it adds no delay to your clock output signal and you don't have to take any provision for it. You can see it as a virtual device which adds zero delay.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks, for your replies. I was unsure about this, because to my external sdram I have got this clock driver in the clock circuit path on my circuit board, but there is no component in my data circuit path. So I expected, that I must tell the TimeQuest in any way, that the path in relation is delayed. If you now say, that there is no added delay for the clock output, I will just ignore the driver and not constrain the path.

    Thanks.