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Honored ContributorTrue Dual Port Ram Synthesizes error with two clock signals
Hello,
well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: Cannot synthesize dual-port RAM logic "ram" where 'ram' being : shared variable ram : memory_t; , well the problem is that when i use two clocks it gives this error, but when i use single clock, all goes well and i get no error. any thoughts over this problem? well the configuration of my system is, that i am using a Cyclone III - ep3c16q240 device, and first i want to test this RAM module alone, and further i will integrate it with my core, and then two different systems will be accessing this RAM with their specific clock. so this is the reason i need two clocks. will be looking forward for the support. thanks for your time. regards Ammar22 Replies
Altera_Forum--- Quote Start --- Do you mean four clocks for the dual port ram in total? That's not supported. --- Quote End --- no, sorry its a typo, i wanted to say i need two separate clocks one for each port. and yes i have checked the Cyclone III hand book, and it supports true-dual port ram with two clock inputs for each port. but i get this error. well okay i will then move to quartus MegaWizard, and will update results then.- Altera_Forum--- Quote Start --- use two separate clock input for each port --- Quote End --- Do you mean four clocks for the dual port ram in total? That's not supported. You should check in the Cyclone III hardware manual, if your intended configuration is feasible with this FPGA. Also the Quartus MegaWizard is a convenient tool to evaluate the possible configurations. If you know that the configuration is supported, but you have difficulties to infer it from VHDL code, try the Quartus language templates.
