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Altera_Forum's avatar
Altera_Forum
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15 years ago

True Dual Port Ram Synthesizes error with two clock signals

Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Do you mean four clocks for the dual port ram in total? That's not supported.

--- Quote End ---

no, sorry its a typo, i wanted to say i need two separate clocks one for each port.

and yes i have checked the Cyclone III hand book, and it supports true-dual port ram with two clock inputs for each port. but i get this error.

well okay i will then move to quartus MegaWizard, and will update results then.