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Altera_Forum
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15 years ago

True Dual Port Ram Synthesizes error with two clock signals

Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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use two separate clock input for each port

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Do you mean four clocks for the dual port ram in total? That's not supported.

You should check in the Cyclone III hardware manual, if your intended configuration is feasible with this FPGA. Also the Quartus MegaWizard is a convenient tool to evaluate the possible configurations. If you know that the configuration is supported, but you have difficulties to infer it from VHDL code, try the Quartus language templates.