Honored ContributorSeems like invoking true dual port (2 R/W ports) doubles the M20K resources - is this correct and if so where is it documented?
I don't see it mentioned in https://www.altera.com/en_us/pdfs/literature/ug/ug_ram_rom.pdf
Honored ContributorA similar thing occurred with Cyclone II, see CYCLONEII_SAFE_WRITE.
1. Tell which device and Quartus versions you are using 2. Check respective errata docHonored ContributorHi,
Are trying to say that ->for example, we have used 256 bit in chip memory parameter(i.e 8-bits and 32 bytes) after full compilation Total block memory bits in flow summary is showing 512? No, You need to check the design files and on-chip memory parameters. can you recheck it? you can compare the parameter setting summary reports with attached.https://www.alteraforum.com/forum/attachment.php?attachmentid=15196 https://www.alteraforum.com/forum/attachment.php?attachmentid=15197 Let me know if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)Honored ContributorHow did you infer the memory block? If you inferred it from HDL, it's possible that you did it in a way that couldn't be synthesized with a single block. Did you have a look at the recommended hdl coding styles (https://www.altera.com/en_us/pdfs/literature/hb/qts/qts_qii51007.pdf) document? They show you how to write your HDL to be sure the synthesizer will pick it up as a single block with dual port.
Honored ContributorFrom all the responses I can see that I was not clear enough about the implementation details, further below:
Quartus Pro Version 17.1 - fails same in 16.x Method: IP Parameter Editor IP: RAM 2-Port Words: 512 Width: 32-40 Block type: M20K All else: defaults, except... Operation Mode - 1R1W - 1x M20K - 2RW - 2x M20K - as reported by fitter My project is the IP only with all ports virtual for experimental purposes. I have attached the .qsys file for your perusal. Disregard the name - just build with either operation mode above and you will duplicate my results. Thanks, TomHonored ContributorArnand, Sorry - I cannot read these images - do you have higher res? ~Tom
Honored ContributorDocumentation is here:
http://quartushelp.altera.com/17.1/index.htm#reference/glossary/def_m20k.htm where it claims that the single M20K width is restricted to 20b when in true dual port mode. I speculate that the RAM cell shadows the memory contents in two halves and does some internal magic to appear as true dual port. I just wish Altera was more explicit about the cost for using it.Honored ContributorHonored ContributorWhat do you mean "not possible" FvM? Do you have inside information on how the true dual-port feature is implemented? If so please enlighten me.
Yes, Table 2-9 confirms the information in the link I provided. However, there is no mention of this restriction in the ug_ram_rom.pdf. If you have a user guide for RAM/ROM it would be very helpful to provide the restrictions on usage there of.Honored ContributorBy nature of a dual-port RAM, their can be only one storage cell for each bit, in so far it's not possible that two single port RAMs mimic a dual port RAM.
--- Quote Start --- However, there is no mention of this restriction in the ug_ram_rom.pdf. If you have a user guide for RAM/ROM it would be very helpful to provide the restrictions on usage there of. --- Quote End --- Yes, it would be helpful. I see however, that the user guide only specifies the parameter ranges, but not the available combinations. It's only listed in the device handbook.Honored ContributorWhich is not what I claimed in my speculation post either. I guess we can terminate this miscommunication now.
