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Altera_Forum's avatar
Altera_Forum
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15 years ago

trouble while using two video source with DE2-70 board

hi!

i am working for a project with DE2-70 board. i need two video input and one video output for my project want to switch video sources and also display two video frame by frame on the same screen.

i used DE2-70_TV demo for the first video source and applied for the second source. And combine these two video blocks. But there is some problems i couldn't solve. In my solution, the two blocks use the same PLL and iTD1_CLK and iTD2_CLK are being switcehed by this PLL .

The blocks are working when i used seperately. But it doesn't work when i combine these two blocks? If you have any idea, can you share with me?

(Maybe i can learn something from DE2_70_TV_PIP demonstaration but it is encrypted so i couldnt see the code.)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In addition to this, i am trying to use SignalTap II logic analyzer tool. to observe the signals.

    In signalTap II logic analyzer settings, when i set iTD1_CLK27 as clock, the video from the first video source is working perfectly, but the second one is not.

    When i set iTD2_CLK27 as clock for SignalTap II settings, this time the video from coming from the second video source is working perfectly, but the first one is not.

    I thought that, there is a timing problem in my design. Because There is no change in my code, by only changing Signal Tap II settings, the expected result can be changed. i just want to see both of video coming from the two source by switching between them.

    Any idea will be very usefull for me. THanks...
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes it looks like a timing problem. First check that all your inputs/outputs are constrained correctly, that all your clock inputs are correctly defined, and then check the Timequest report.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    i think i have solved the problem for now.

    From Assignments >> Settings >> Fitter Settings , you will also find an "Optimize hold timing" check. By changing its value to "All Paths" "Clock Hold:'iTD2_CLK27' " violation is removed and my design worked well.

    But, iTD2_CLK7 which is a dedicated external clock pin for the FPGA is still looks like not being used as global signal when i looked at the fitter resource report. i dont understand why but i think there is no problem for now :)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You can force the clock to use a global signal resource in the assignment editor, but if you meet all timing requirements like that you don't need to.

    With the default settings I think that the fitter automatically promotes a clock that needs it to a global signal.