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Altera_Forum's avatar
Altera_Forum
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15 years ago

trouble while using two video source with DE2-70 board

hi! i am working for a project with DE2-70 board. i need two video input and one video output for my project want to switch video sources and also display two video frame by frame on the same scre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

i think i have solved the problem for now.

From Assignments >> Settings >> Fitter Settings , you will also find an "Optimize hold timing" check. By changing its value to "All Paths" "Clock Hold:'iTD2_CLK27' " violation is removed and my design worked well.

But, iTD2_CLK7 which is a dedicated external clock pin for the FPGA is still looks like not being used as global signal when i looked at the fitter resource report. i dont understand why but i think there is no problem for now :)