Trouble interfacing FLASH pins to GPIO (retro game related)

Hey all,

Just got an Altera DE1 dev board using the Cyclone II, and I'm working on a simple test that is literally just connecting the FLASH chip to the GPIO_0 bus. I'm not performing any logic, but the FLASH does have code I wrote to it using the DE Control panel, and I've verified my code is correct.

This is a test to send a small test ROM file from the DE1 to the GPIO ports which are connected to a Super Nintendo cartridge. I've done similar tests with Xilinx CPLD before (data lines ran direct to system, but address and control lines ran to CPLD), but this is my first foray into sending all pins through a FPGA.

My problem is that the game will not boot! I've double and triple checked my wiring, and that's good. Each pin on the SNES just connects to one of the corresponding GPIO pins, which is routed to the FLASH pins through the FPGA. I've never run data lines through a PLD before, so I don't know if there is something special that they need in contrast to a regular address line? Or is there something glaringly obvious that I'm missing?

I've attached my code in hopes someone can help me out.

Also, I've already added FL_CE_N into my pin assignments as I noticed that it was missing originally.

library ieee;use ieee.std_logic_1164.all;
entity mapper is
	port( 
	FL_ADDR  : out std_logic_vector(21 downto 0) ;
	FL_DQ    : out std_logic_vector(7 downto 0) ;
	FL_CE_N  : out std_logic;
	FL_OE_N  : out std_logic;
	FL_RST_N : out std_logic;
	FL_WE_N  : out std_logic;
	GPIO_0   : inout std_logic_vector(35 downto 0) 
	
	);
	
end mapper;
architecture arch of mapper is
begin
	--CONTROL LINES
	FL_CE_N <= '0';
	FL_OE_N <= '0';
	FL_RST_N <= '1';
	FL_WE_N <= '1';
	--DATA LINES
	FL_DQ(7 downto 0) <= GPIO_0(21 downto 14);
	-- ADDRESS LINES
	FL_ADDR(17) <= GPIO_0(2);
	FL_ADDR(16) <= GPIO_0(24);
	FL_ADDR(15) <= GPIO_0(4);
	FL_ADDR(14) <= GPIO_0(29);
	FL_ADDR(13) <= GPIO_0(28);
	FL_ADDR(12) <= GPIO_0(5);
	FL_ADDR(11) <= GPIO_0(25);
	FL_ADDR(10) <= GPIO_0(23);
	FL_ADDR(9) <= GPIO_0(26);
	FL_ADDR(8) <= GPIO_0(27);
	FL_ADDR(7) <= GPIO_0(6);
	FL_ADDR(6) <= GPIO_0(7);
	FL_ADDR(5) <= GPIO_0(8);
	FL_ADDR(4) <= GPIO_0(9);
	FL_ADDR(3) <= GPIO_0(10);
	FL_ADDR(2) <= GPIO_0(11);
	FL_ADDR(1) <= GPIO_0(12);
	FL_ADDR(0) <= GPIO_0(13);
	
end arch;

Any ideas and help here would be greatly appreciated, thanks!