Triple-Speed Ethernet - Verilog TX/RX example

Hi Varban,

There are few simple option available in Intel website for Verilog Design Example. You may refer to it.

Kindly do let me know if you needed further support.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/verilog.html

Regards,

Pavee

Hi,

Good day to you.

I believe you're working with Cyclone 10 devkit with TSE IP. We do have a reference design for TSE IP. Link provided below.

Kindly do let me know if you've tried this.

https://www.intel.com/content/www/us/en/design-example/714768/cyclone-10-lp-intel-fpga-triple-speed-ethernet-and-intel-on-board-phy-chip-reference-design.html

Regards,

Pavee

Hi Pavee,

Yes, exactly, my question is based on the TSE IP and the official example for the Cyclone 10 LP that you have mentioned.

I am able to compile the IP, flash the FPGA over the USB-to-JTAG and run all of the TCL tests from the System Console.

However, I do not want TCL and Avalon-ST.

I need simple Verilog examples on top of the TSE IP, with send/receive FSM funcionality.

Hi Varban,

Thanks for confirming. Unfortunately, we don't have example design based on your requirement.

I believe you can refer to UG below. It has prompt explanation on State machine Verilog.

https://www.intel.com/content/www/us/en/docs/programmable/683082/22-3/verilog-hdl-state-machines.html

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get the support from Intel experts.

Otherwise, the community users will continue to help you on this thread.

Thank you.