Total logic elements increasing

Question

Hi,

I'm working with EP3C16F484C6, Cyclone 3 FPGA.

I wrote a code that has ~24% Total logic elements.

When I wrote several I/O names under the entity, port, the Total logic elements jump to 83% (?!) (Total combination functions: 80%). before that I used those pins as signal in the architecture.

Those signal I/O getting their data etch telegram that received correctly through UART (every ~50msec).

In the architecture, I tried to assign the signals inside the code to another names that signed directly the Port- no good- still 83%.

Can anybody know/guess what the problem could be?

Thanks,

Idan

altera_forum · Answer

I gues it is a situation like this example:

You design a system that runs two modes: qpsk,16qam options. if I declare a signal called mode as pin then the compiler is forced to respect my options.

if I set mode as internal signal then the mode will be static and defaults to one case, the other case is optimised off.

altera_forum · Answer

Hi kaz, In the architecture, I tried to assign the signals inside the code to another names that signed directly the Port- no good- still 83%. What do you think I should do? Idan

altera_forum · Answer

The problem is probably one with your design rather than an error in the compiler. The solution would be to investigate which entities are eating all the logic and find out why.

altera_forum · Answer

If my guess applies then there is nothing wrong. You don't need to worry, just connect your inputs as they should be.

Let me rephrase what might happened; an input port at top of project is assigned a pin by compiler. To the compiler a input port will get its drive from outside and so is non-static and must be respected...

On the other hand an internally declared signal instead of port may be static unless driven from outside indirectly. By static I mean undriven internal node which may default to zero. In this case all the logic related to the case of '1' will be removed because the compiler sees it is never going to occur.

altera_forum · Answer

Hi,

In addition to the problem above, when I’m compiling the code I get the following "Critical Warning: Synopsys Design Constrain File not found: “top level entity name.sdc”".

What does it mean, is it possible that the capacity problem (80%) is related to that warning?

Idan

Forum Discussion

Total logic elements increasing

6 Replies

Recent Discussions

Trouble Getting started with Stratix 10 SOC

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered

License Server new License File

Does the 1SG280LU2F50E2VG support bitfile encryption