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Altera_Forum
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15 years ago

Total logic elements increasing

Hi, I'm working with EP3C16F484C6, Cyclone 3 FPGA. I wrote a code that has ~24% Total logic elements. When I wrote several I/O names under the entity, port, the Total logic elements ju...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I gues it is a situation like this example:

You design a system that runs two modes: qpsk,16qam options. if I declare a signal called mode as pin then the compiler is forced to respect my options.

if I set mode as internal signal then the mode will be static and defaults to one case, the other case is optimised off.