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Altera_Forum
Honored Contributor
Honored ContributorTotal logic elements increasing
Hi, I'm working with EP3C16F484C6, Cyclone 3 FPGA. I wrote a code that has ~24% Total logic elements. When I wrote several I/O names under the entity, port, the Total logic elements ju...
Altera_ForumHonored Contributor
Honored ContributorThe problem is probably one with your design rather than an error in the compiler. The solution would be to investigate which entities are eating all the logic and find out why.
