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Altera_Forum
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14 years ago

Total logic elements increasing

Hi, I'm working with EP3C16F484C6, Cyclone 3 FPGA. I wrote a code that has ~24% Total logic elements. When I wrote several I/O names under the entity, port, the Total logic elements ju...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The problem is probably one with your design rather than an error in the compiler. The solution would be to investigate which entities are eating all the logic and find out why.