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Altera_Forum
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14 years ago

Total logic elements increasing

Hi, I'm working with EP3C16F484C6, Cyclone 3 FPGA. I wrote a code that has ~24% Total logic elements. When I wrote several I/O names under the entity, port, the Total logic elements ju...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi,

In addition to the problem above, when I’m compiling the code I get the following "Critical Warning: Synopsys Design Constrain File not found: “top level entity name.sdc”".

What does it mean, is it possible that the capacity problem (80%) is related to that warning?

Idan