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Altera_Forum
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15 years ago

Total logic elements increasing

Hi, I'm working with EP3C16F484C6, Cyclone 3 FPGA. I wrote a code that has ~24% Total logic elements. When I wrote several I/O names under the entity, port, the Total logic elements ju...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

No. This is because you are using Timequest and you dont have a constraints file. This will see if your design can meet the required timing.

It has no effecct on resource usage - only your source code controls that.