Honored ContributorHello,
We are designing a system that is successfully generated in SOPC builder and compiled in Quartus II. The system clock is 75 MHz and we need to speed up the NIOS II processing power by increasing only NIOS II frequency, therefore it is raised from 75 MHz to 150 MHz. After doping so, the timing requirements become not met. Can any one advise me in this issue. Thanks & Regards.
Honored ContributorPlease use the "timing design advisor" to see what you can do about it.
You can find out more in the user manualHonored Contributoradd an Avalon memory mapped pipeline bridge between the Nios data/instruction masters and the Nios JTAG debug module (not the jtag uart). The debug module without a pipeline usually slows down your system.
Then check if you should add more pipelines in your system. Multiple masters and/or multiple slaves connected together tend to reduce the max frequency of the system, and adding pipelines at strategic places can help increase fmax, at the expense of a higher latency.Honored ContributorHonored ContributorHonored ContributorIf you have negative setup slack, open the top failing paths list in timequest and try to figure out the origin and the destination of the path. Then look if you can add another pipeline bridge on that path.
If you have negative hold slack, open the fitter settings and check that you have the optimize corner timing option enabled on all paths.
