Timing requirement not met after increasing NIOS frequency

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add an Avalon memory mapped pipeline bridge between the Nios data/instruction masters and the Nios JTAG debug module (not the jtag uart). The debug module without a pipeline usually slows down your system.

Then check if you should add more pipelines in your system. Multiple masters and/or multiple slaves connected together tend to reduce the max frequency of the system, and adding pipelines at strategic places can help increase fmax, at the expense of a higher latency.

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Hello,

Thank you very much for your reply.

I followed your suggestions and started first by inserting an Avalon-MM pipeline bridge between the NIOS II data/instruction masters and the JTAG debug module, unfortunately the slack values become slightly worser :(. Do you have an explanation to that.

Kind Regards