Timing requirement not met after increasing NIOS frequency

add an Avalon memory mapped pipeline bridge between the Nios data/instruction masters and the Nios JTAG debug module (not the jtag uart). The debug module without a pipeline usually slows down your system.

Then check if you should add more pipelines in your system. Multiple masters and/or multiple slaves connected together tend to reduce the max frequency of the system, and adding pipelines at strategic places can help increase fmax, at the expense of a higher latency.