Timing closure

The relevant part of my circuit is shown in figure "figure.jpg".

There are two timing violations in my system. Both include one of the counter registers and two states in the FSM.

From TimeQuest, the failing node associated with the counter-register is labelled *_RTM018.

I can close timing by inserting a DFF between the "ageb"-output and the "flag"-input on the FSM.

(I don't know the exact term here, but I refer to this as "re-clocking" the flag.)

However, if I do so then my system performance will be degraded.

According to the Timing Optimization Advisor, I can reduce delay by using "Fast input/output/output-enable registers".

When clicking "list all registers", my *_RTM018 node shows up as an input register. Hence, I try to assign the *_RTM018 register as a "fast-input register".

To do this, I use the Assignment Editor, but I cannot find the correct node when using the Node Finder.

If I apply the "Fast Input Register" to the register without the _RTM018 label, then Quartus throws an "Ignored Fitter Assignment" with comment that the node is not a simple register. If I apply it to the full node-name, i.e. *_RTM018, then the Assignment Editor cannot recognize it.

The snipping "failingPath.jpg" shows the one of the two failing paths, with nodes highlighted in red.

The delay between them is 20.9 ns, which is to slow for my 50 MHz clock.

Is it possible to assign this register, i.e. "sCntVal[1]_RTM018" as a Fast Input Register, and thereby reducing the path delay ? If so, then how can I do this ?

If the *_RTM018 register cannot be optimized, then is there a better way than to "re-clock the flag" to close timing ?