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Altera_Forum's avatar
Altera_Forum
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7 years ago

Timing closure

The relevant part of my circuit is shown in figure "figure.jpg". There are two timing violations in my system. Both include one of the counter registers and two states in the FSM. From TimeQuest...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

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Fast IO registers are only meant for Device Pins. With fast IO registers you cannot have logic before the register. Do some of the inputs come from pins? And if they do, why are they not synchronised to the clock first?

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I suspected that fast IO registers are for IOs only...

My inputs are fed through a simple two-stage synchronizer. The figure only shows the part of the circuit that involves the largest delay.