New Contributor
Regular ContributorHi Sumanth,
Thank you for sharing these observations. To help us narrow down the root cause, could you please clarify a few details:
Quartus Settings
- Are both designs using the same Remote Update IP version and Quartus Prime Pro settings?
- Is the “Auto-restart configuration after error” option enabled in both cases?
Flash Content and Address
- When triggering reconfiguration from an unprogrammed location, is the start address set to 0x00 or another value?
- Is the factory image correctly placed at 0x20 (as recommended in the user guide)?
Error Handling Signals
- On the device that stalls (10CX105YF672I5G), do you see nSTATUS or any error indication toggling before the stall?
- Does the watchdog timer feature play any role in your design?
Clock and Reset
- Is the Remote Update IP clock stable during reset and reconfiguration?
- Are you using the same reset sequence for both devices?
These details will help us confirm whether this is a device-level difference or a configuration setting issue.
Regards,
Fakhrul
New ContributorThank you for the questions. Below are my answers:
- Are both designs using the same Remote Update IP version and Quartus Prime Pro settings?
Yes. Remote update Ip version 19.1.0
- Is the “Auto-restart configuration after error” option enabled in both cases?
Yes.
- When triggering reconfiguration from an unprogrammed location, is the start address set to 0x00 or another value?
In the project I am working on, we are using the MT25QU512 flash. The application image address is set to 0x00C00000, and the base image address is set to 0x00010000 to align with the sector boundary. This configuration is the same on both boards, and it works fine.
- Is the factory image correctly placed at 0x20 (as recommended in the user guide)?
No. I have set it to 0x00010000 to align with the sector boundary.(MT25QU512 flash). We use a different mechanism for Image updates
- On the device that stalls (10CX105YF672I5G), do you see nSTATUS or any error indication toggling before the stall?
After reconfiguration, we observed that the conf_done signal was not yet asserted.
- Does the watchdog timer feature play any role in your design?
Yes, We have a logic to reset watchdog timer before it gets timeout.
Clock and Reset
- Is the Remote Update IP clock stable during reset and reconfiguration?
Yes
- Are you using the same reset sequence for both devices?
Yes. To work properly on 10CX150YF672E5G FPGA we have currently modified reset sequence to wait for 300us.
