Hello, In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signals on the bus indicate Data or Address . As the logic is checking for the edges on WRN and ALE in a process, Quartus thinks they are clocks and gives timing errors: "WRN and ALE are clocks and they are not constrained". How do I solve this issue having known that WRN and ALE are not clocks?

Set the signals as false paths.

Yes, I had set false paths on them. But Timing analyzer report still shows these two signals as unconstrained clocks in the clock status summary. My Code: --somewhere in the architecture PROCESS ( ale, adbus )BEGIN IF ( ale'event AND ale = '0' ) THEN address <= adbus; END IF ;END PROCESS; PROCESS ( wrn, clearn, adbus )BEGIN IF clearn = '0' THEN data<= "0000000000000000" ; ELSIF ( wrn'event AND wrn = '1' ) THEN data <= adbus( 15 DOWNTO 0 ); END IF ; END PROCESS I am using the edges of ALE and WRN to identify if it is address or data on the adbus, and the tool thinks these are clocks. There are also warnings: Warning (332060): Node: wrn was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: ale was determined to be a clock but was found without an associated clock assignment.

You're coding them like clocks so the tool will think they're clocks. What do your false path constraints look like?

The false path constraints are as follows: set_false_path -from [get_ports WRN] set_false_path -from [get_ports ALE]

I think as long as you are using edges instead of logic levels for these control signals, the tool will still look at these as clocks. Is there a reason why you must do this and can't just turn these processes into combinatorial logic instead of registers?

Timing analysis error on Asynchronous control signals

23 Replies

SyafieqS
Super Contributor
4 years ago
Hi Naveen,

Are the signal still being ignored if you change the constraint from set_false_path to set_clock_group? I noticed that this is a asynchronous control signals.
SyafieqS
Super Contributor
4 years ago
Hi Naveen,

Let me know if there is any update from previous reply?
Are you able to constrain the clocks?
- NShan12
  Occasional Contributor
  4 years ago
  Hello @SyafieqS , sorry for a delayed reply. Held up with too many topics.
  
  To replace false path to clock groups, I should first create clock constraints on WRN and ALE. This is as per Intel's example set clock groups constraint:
  
  But since ALE and WRN are just address latch and write enable signals they do not have a clock period. So, I do not know how to write a generate clock constraint on ALE and WRN.
  
  The below screenshot shows the behaviour of ALE and WRN during a bus write cycle:
  
  Thank you.
SyafieqS
Super Contributor
4 years ago
We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
sstrell
Super Contributor
4 years ago
If your code from 11/2/21 is still the same, you are still coding these signals like clocked processes instead of combinatorial logic. You should look at adjusting your code such that the signals no longer look like clock signals to the compiler.
- NShan12
  Occasional Contributor
  4 years ago
  Hello @sstrell ,
  
  Alright. Thank you very much for your support. This issue can now be closed.

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Timing analysis error on Asynchronous control signals

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