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Altera_Forum's avatar
Altera_Forum
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14 years ago

TimeQuest Timing Analyzer issues

I'm having problems figuring out how to work with this TimeQuest Timing Analyzer. I previously upgraded to a stratix IV from a Stratix III so I am forced to use TimeQuest instead of the classic analyzer. I can describe the problem 3 steps:

1. The analyzer doesn't always identify the clocks in my design. I have a a pll generating several (quite obvious) clocks. I'm also using the signal tap to capture a few waveforms. It identifies the altera_reserved_tck which I believe is what is used for the signal tap jtag communication and that's it. What happens to all the other clocks in my design? I can't know If I'm making timings or not.

2. If I disable the signal tap and recompile, then I do see all my clocks in the TimeQuest Timing Analyzer. Then I realize that according to the analyzer I'm not making timings.

3. But according to the TimeQuest Analyzer, my Fmax exceeds my requirements (assumed to be the PLL designed output clocks). I am failing in the Setup summary. How can I not meet a setup requirement but have an Fmax that exceeds my requirements. This doesn't make any sense.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Use 'derive_pll_clocks -create_base_clocks' in TimeQuest to create your clock constraints. You can type this in the console window, or put it in an .sdc file and add it to the project.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Go to alterawiki.com, Popular on the left, and there's a TimeQuest User Guide. The first chapter is Getting Started and will talk about a basic .sdc setup.

    TAN would run without any assignments, but had to make assumptions(which admittedly were right most of the time, but painful when they were wrong, especially because most users don't understand the assumptions). TimeQuest makes you add constraints to do proper timing analysis, but it's not much more than:

    create_clock -period 10.0 -name clkname [get_ports {fpga_clk_port}]

    derive_pll_clocks

    derive_clock_uncertainty

    and possibly a set_clock_groups assignment if you have unrelated clocks.

    (I am in the habit of constraining my input clocks with a create_clock assignment. Jimbo suggested adding -create_base_clocks to the derive_pll_clocks, which will do the same thing, it just won't constrain input clocks that aren't hooked up to a PLL,because it wouldn't know their period). There is a bit of a learning curve, but should be well worth it. Good luck.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Alright, I'll take up on some of your suggestions. I'll come back if I have more problems.

    thanks,