TimeQuest Timing Analyzer issues

Go to alterawiki.com, Popular on the left, and there's a TimeQuest User Guide. The first chapter is Getting Started and will talk about a basic .sdc setup.

TAN would run without any assignments, but had to make assumptions(which admittedly were right most of the time, but painful when they were wrong, especially because most users don't understand the assumptions). TimeQuest makes you add constraints to do proper timing analysis, but it's not much more than:

create_clock -period 10.0 -name clkname [get_ports {fpga_clk_port}]

derive_pll_clocks

derive_clock_uncertainty

and possibly a set_clock_groups assignment if you have unrelated clocks.

(I am in the habit of constraining my input clocks with a create_clock assignment. Jimbo suggested adding -create_base_clocks to the derive_pll_clocks, which will do the same thing, it just won't constrain input clocks that aren't hooked up to a PLL,because it wouldn't know their period). There is a bit of a learning curve, but should be well worth it. Good luck.