TimeQuest .sdc constraints for EPCS (ALTASMI_PARALLEL megafunction)

Here is what I got so far:

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# Create external XTAL Clock input

create_clock -name {CLK_50MHZ_PLL[4]} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLK_50MHZ_PLL[4]}]

# Create PLL Generated Clocks 100MHz and 25MHz

create_generated_clock -name {clk} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLK_50MHZ_PLL[4]} [get_pins {pll|altpll_component|auto_generated|pll1|clk[0]}]

create_generated_clock -name {clk_asmi} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 2 -master_clock {CLK_50MHZ_PLL[4]} [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}]

# Constrain the *ALTERA_DCLK output port from the ALTASMI_PARALLEL megafunction

set_min_delay -from [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_ports {*ALTERA_DCLK}] 5.1

set_max_delay -from [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_ports {*ALTERA_DCLK}] 7.1

# EPCS clk (virtual clock at the input pin of the EPCS device)

create_generated_clock -name {clk_epcs} -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {*ALTERA_DCLK}]

set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 0.2

# Set Clock Uncertainty

derive_clock_uncertainty

# Board trace delays

set max_btd 0.2

set min_btd 0.1

# Set Input Delay, see Table 3-17 of the EPCS Datasheet# **************************************************************

set_input_delay -max [expr $max_btd +8 +$max_btd] -clock { epcs_dclk } -clock_fall [get_ports {*ALTERA_DATA0}]

set_input_delay -min [expr $min_btd +5 +$min_btd] -clock { epcs_dclk } -clock_fall [get_ports {*ALTERA_DATA0}]

# Set Output Delay, see Table 3-16 of the EPCS Datasheet# **************************************************************# Do not violate tSLCH (t ce setup)

set_output_delay -add_delay -max -clock [get_clocks {clk_epcs}] [expr +$max_btd +10 -$min_btd] [get_ports {*ALTERA_SCE}]# Do not violate tCHSL (t ce hold)

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd +10 -$max_btd] [get_ports {*ALTERA_SCE}]

# Do not violate tDVCH (t data setup)

set_output_delay -add_delay -max -clock [get_clocks {clk_epcs}] [expr +$max_btd +5 -$min_btd] [get_ports {*ALTERA_SDO}]# Do not violate tCHDX (t data hold)

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd +5 -$max_btd] [get_ports {*ALTERA_SDO}]

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When I use the "set_max_skew" like shown above I get:

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Warning: No path is found satisfying assignment "set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1.000 ". This assignment will be ignored.

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When I remove the "set_max_skew" line I get:

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Unconstrained Output Port:

asmi_slave:asmi_inst|asmi:asmi_inst|asmi_altasmi_parallel_t852:asmi_altasmi_parallel_t852_component|cycloneii_asmiblock3~ALTERA_DCLK

No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.

Unconstrained Output Port Paths:

pll|altpll_component|auto_generated|pll1|clk[1]

No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.

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So how do I fix it ? Is it a bug in Quartus ?

There seems to be two different clocks in these statements:

# EPCS clk output

create_generated_clock -name {epcs_dclk} -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {*ALTERA_DCLK}]

set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1

Was that intended?

I would think you might have ment something more like this:

# EPCS clk output

create_generated_clock -name {clk_epcs} -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {*ALTERA_DCLK}]

set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1

In order for the "set_max_skew" command to be applied to the design by the tools.

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ngcreese, you are correct. I had a copy paste error in the forum, (I corrected it now) but the .sdc file that I used with TimeQuest was correct. So Your tip did not help me.

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No worries man. Glad your constraints are working for you without this skew constraint.

No, that is the problem. It seams they do not work with it but also do not work without it.

I filed a service request with altera, let's see what they say about it.

one other question for you. It seems that on your output delays, you're using a system view, accounting for board data delay, setup & hold values of the external device and board clk delays. With that view of the outside world I've read that -max -min formulas look like this:

Output max delay = max(board_data_delay) + tsu_ext - min(board_clk_delay)

Output min dalay = min(board_data_delay) - th_ext - max(board_clk_delay)

Did you intend to have positive tH values in your assertion expressions, as shown in bold and italicized below?

# Board trace delays

set max_btd 2

set min_btd 1

# Set Output Delay, see Table 3-16 of the EPCS Datasheet# ************************************************* *************# Do not violate tSLCH (t ce setup)

set_output_delay -add_delay -max -clock [get_clocks {clk_epcs}] [expr +$max_btd +10 -$min_btd] [get_ports {*ALTERA_SCE}]# Do not violate tCHSL (t ce hold)

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd +10 -$max_btd] [get_ports {*ALTERA_SCE}]

# Do not violate tDVCH (t data setup)

set_output_delay -add_delay -max -clock [get_clocks {clk_epcs}] [expr +$max_btd +5 -$min_btd] [get_ports {*ALTERA_SDO}]# Do not violate tCHDX (t data hold)

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd +5 -$max_btd] [get_ports {*ALTERA_SDO}]

*****

Your setup (-max) formulas looks good. However, I'm wondering if your hold (-min) formulas are correct.

Appying the system view formula from above:

Output min dalay = min(board_data_delay) - th_ext - max(board_clk_delay)

I thinking your output delay -min statements should look like this:

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd -10 -$max_btd] [get_ports {*ALTERA_SCE}]

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd -5 -$max_btd] [get_ports {*ALTERA_SDO}]

What's your thoughts on this?

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Did you noticed that I have a - sign before the [expr ] ?

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Didn't notice them, but I don't believe they should be there.

You're current expressions:

# Board trace delays

set max_btd 2

set min_btd 1

-[expr +$min_btd +10 -$max_btd]

-[ 1 + 10 - 2 ]

-[ 11 - 2 ]

-[ 9 ]

-9

-[expr +$min_btd +5 -$max_btd]

-[ 1 + 5 - 2 ]

-[ 6 - 2 ]

-[ 4 ]

-4

What the system view, source sync docs seem to be saying (no leading minus sign on the entire expression,instead tH value itself is negated):

[expr +$min_btd -10 -$max_btd]

[ 1 - 10 - 2 ]

[ -9 - 2 ]

[ -11 ]

-11

[expr +$min_btd -5 -$max_btd]

[ 1 - 5 - 2 ]

[ -4 - 2 ]

[ -6 ]

-6

The results do seem to work out differently. Tbh, I havent seen versions of these -max -min equations where the -min [expr... ] has started off with a negative sign.