TimeQuest .sdc constraints for EPCS (ALTASMI_PARALLEL megafunction)

one other question for you. It seems that on your output delays, you're using a system view, accounting for board data delay, setup & hold values of the external device and board clk delays. With that view of the outside world I've read that -max -min formulas look like this:

Output max delay = max(board_data_delay) + tsu_ext - min(board_clk_delay)

Output min dalay = min(board_data_delay) - th_ext - max(board_clk_delay)

Did you intend to have positive tH values in your assertion expressions, as shown in bold and italicized below?

# Board trace delays

set max_btd 2

set min_btd 1

# Set Output Delay, see Table 3-16 of the EPCS Datasheet# ************************************************* *************# Do not violate tSLCH (t ce setup)

set_output_delay -add_delay -max -clock [get_clocks {clk_epcs}] [expr +$max_btd +10 -$min_btd] [get_ports {*ALTERA_SCE}]# Do not violate tCHSL (t ce hold)

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd +10 -$max_btd] [get_ports {*ALTERA_SCE}]

# Do not violate tDVCH (t data setup)

set_output_delay -add_delay -max -clock [get_clocks {clk_epcs}] [expr +$max_btd +5 -$min_btd] [get_ports {*ALTERA_SDO}]# Do not violate tCHDX (t data hold)

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd +5 -$max_btd] [get_ports {*ALTERA_SDO}]

*****

Your setup (-max) formulas looks good. However, I'm wondering if your hold (-min) formulas are correct.

Appying the system view formula from above:

Output min dalay = min(board_data_delay) - th_ext - max(board_clk_delay)

I thinking your output delay -min statements should look like this:

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd -10 -$max_btd] [get_ports {*ALTERA_SCE}]

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd -5 -$max_btd] [get_ports {*ALTERA_SDO}]

What's your thoughts on this?