TimeQuest .sdc constraints for EPCS (ALTASMI_PARALLEL megafunction)

There seems to be two different clocks in these statements:

# EPCS clk output

create_generated_clock -name {epcs_dclk} -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {*ALTERA_DCLK}]

set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1

Was that intended?

I would think you might have ment something more like this:

# EPCS clk output

create_generated_clock -name {clk_epcs} -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {*ALTERA_DCLK}]

set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1

In order for the "set_max_skew" command to be applied to the design by the tools.